Image processing generally involves use of pixel values that are stored in a memory. Pixel values for different pixel locations are stored at different memory locations. Various mappings of pixel locations to memory locations can be used. Such mappings have a considerable effect on image processing. US 2005/0083337 describes how memory access speed can be improved by suitable mapping. WO 2005/104027 describes a memory access circuit that compensates for mapping when pixels values for a plurality of pixel locations are used in parallel as operands for image processing operations.
US 2005/0083337 describes an image processing system that provides for alternate ways of storing image data in a memory. Different image processing algorithms require access to pixel values according to different sequences of pixel locations. Thus for example display of an image requires reading on a line-by-line basis; image decompression typically requires block-based reading. A memory device is used that provides for faster access to pixel values that are stored consecutively than to pixel values that are stored distributed over different memory parts. As a result access for display purposes can be done most quickly if pixel values along an image line are stored consecutively, but block based access can be done most quickly if pixel values of along successive lines of a block are stored consecutively.
In many applications both display using line based access and decompression using block-based access will be used. US 2005/0083337 supports this by storing pixel values grouped in different ways so that optimal speed can be realized for different forms of access. The grouping depends on parameters such as block width and height, the probability distribution of addresses and on properties of the memory device, such as width of the memory bus and the number of memory banks. When pixel values are written, multiple copies of the pixel values are written, grouped in different ways, according to the way in which the pixel values will be read.
US 2005/0083337 provides for address mapping from logical addresses (e.g. pixel coordinates) to physical addresses in the memory where the data values will be written. Different address mappings are needed to store the pixel values in different groupings. A look-up table memory is provided to describe the mappings. An address generator uses the look up table to generate the physical addresses from the logical addresses. The address mapping is selected based on a determination of the mapping that will result in minimum cost (in terms of access speed) for a given program. US 2005/0083337 is not directed at parallel processing of a plurality of pixel values.
WO 2005/104027 describes an image processing circuit that provides parallel access to pixel values from a working memory. The working memory stores pixels values for a region of pixel locations. Typically the region is part of a larger image for which pixel values are stored in a main memory. In this case, the working memory acts as a cache that stores copies of part of the pixels values from the main memory.
The working memory comprises memory banks that are able to output pixel values in parallel. The parallel-output pixels are supplied to a parallel pixel processor (e.g. a SIMD (Single Instruction Multiple Data) circuit), optionally after intermediate parallel storage in a register of a register file. When the pixel values are supplied in parallel there must be a predetermined relation between positions of the pixel values in the parallel output and the relative positions of the corresponding pixel locations with respect to an addressed image part (e.g. an addressed block).
In WO 2005/104027 pixel values are stored in the working memory wrapped around in line-segment based fashion, pixel values for successive pixel locations along a horizontal line-segment in an image being stored in successive banks, wrapping around from the last memory bank in the succession to the first memory bank in the succession. Pixel values for pixel locations in a segment of the next horizontal line are stored similarly following the pixel values for the previous line segment (optionally aligned to the same memory bank). Typically, the region of pixel locations for which pixel values are stored slides along the image. In this case the memory locations for pixel locations that have slid out of the region can be reused for pixel locations that have slid into the region. Thus, there will be no predetermined memory bank that stores the pixel value for the upper left location in the region.
WO 2005/104027 allows parallel output of pixel values for a block of pixel locations within the stored region. The parallel output is controlled by providing an address of the block in the region (e.g. in terms of the x-y coordinates of the upper left corner of the block). The working memory responds by outputting pixel values from the block at outputs defined by the pixel locations relative to the address of the block. Thus, for example, the pixel value for the location in the upper left corner of the block is output at a first predetermined output and so on.
It is important to note that this type of operation requires a number of parameters to control memory access. For example, there is no predetermined relation between memory banks and locations in addressed blocks. Therefore the coupling of memory banks to outputs has to be controlled dependent on the memory bank wherein the pixel value for a predetermined pixel location in the stored region is stored and the coordinates of the addressed block. Other examples where parameters are needed include the case where the amount of data per pixel location can be varied. For example, in some image processing applications reduced resolution is used for stored color related values in comparison to stored luminance related values. Hence the coupling between banks and output may be different for color and luminance. The same may hold if different quantization accuracy is used for color and luminance. Furthermore, it may be desirable to wrap around storage of pixel values of some images before reaching the full number of memory banks, in order to use the remaining banks to provide for output of another image (or another color component of the same image etc.). This may also complicate the relation between outputs and memory banks.
In the data processing circuit of WO 2005/104027 the necessary parameters are maintained in the memory access circuit. When a block of the memory is accessed the memory access circuit receives the address of the block (e.g. its coordinates) and combines this address with the parameters to select the necessary coupling between memory banks and outputs. Only one set of parameters can be used at a time.